Contemporary processing units are often multi-core processors (MCP) with increasing levels of system-on-a-chip (SoC) capability. Regulatory agencies have yet to identify an acceptable approach to certifying the use of MCPs for handling safety-critical applications in an airborne system. For example, aircraft display systems may incorporate safety-critical applications for compiling critical data parameters and forwarding those parameters to a graphics engine for generating cockpit displays. If such a safety-critical application were to fail, the result would be catastrophic (e.g., probable loss of the aircraft as well as its crew or passengers). Accordingly, architectural mitigations (i.e., fault detection and response) must provide assurance that safety-critical application failures will be extremely improbable (e.g. 10e−9 probability per flight hour). The Certification Authorities Software Team, in its May 2014 position paper “Multi-core Processors” which is herein incorporated in its entirety, identified various challenges and hurdles which preclude the certification of MCP use. For example, the existence of coherency fabrics, interference channels, or the dynamic reallocation of shared system resources may lead to non-deterministic results which preclude the successful execution of safety-critical applications.